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uwindsor.ca

ICDWRBFC

Programmable 15-TAP Hybrid DBNS FIR Filter

Video processing filter which performs 5.4 billion multiplications and additions (MAC) per second using Double Base Number System (DBNS). This chip was designed in 2 weeks from the original concept to final tape-out. Implemented on TSMCs 0.35µm CMOS processes with a size of 16mmx9mm (or 144 000 000µm2)

Primary Designers: Roberto Muscedere and Johanathon Eskritt


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